This invention relates to a semiconductor integrated circuit, more particularly to a bipolar complementary metal-oxide-semiconductor (biCMOS) integrated circuit having shallow n-wells, and to a fabrication method thereof.
The n-wells in a biCMOS integrated circuit are disposed in a p-type epitaxial layer and contain NPN and PMOS transistors. NMOS transistors are created in the p-type epitaxial layer outside the n-wells. The integrated circuit to be considered further comprises an erasable programmable read-only memory (EPROM), the EPROM cells also being disposed in the p-type epitaxial layer outside the n-wells.
FIGS. 1A to 10 illustrate steps in the fabrication of a prior-art biCMOS integrated circuit with EPROM. These steps are carried out by well-known techniques such as photolithography, ion implantation, and chemical vapor deposition (CVD), detailed accounts of which will be omitted. Although these drawings illustrate the fabrication of only one NPN transistor, one PMOS transistor, one NMOS transistor, and one EPROM memory cell, it will be understood that normally large numbers of these active elements are fabricated simultaneously on the same substrate.
With reference to FIG. 1A, a p-type silicon substrate 1 with a specific resistance of substantially 15 ohms. cm is heated to substantially 1000.degree. C. for substantially 20 minutes in an oxygen (O.sub.2) atmosphere to form a silicon dioxide (SiO.sub.2) layer 2 substantially 450 angstroms thick. Next, using photolithographic techniques, the surface is coated with a patterned resist 3 covering areas other than a first area 5 and a second area 6. The first area 5 is an area in which an NPN transistor will be formed. The second area is an area in which a PMOS transistor will be formed. Although only one first area and one second area are shown in the drawings, most integrated circuits will have many first areas and many second areas, the steps described below being carried out on all first areas and all second areas simultaneously.
After creation of the resist 3, antimony ions 4 are implanted at an accelerating voltage of 40 keV and dose of 3.times.10.sup.15 ions/cm.sup.2 into the silicon substrate 1 in the first area 5 and the second area 6.
With reference to FIG. 1B, next the resist 3 is removed and the substrate is heated to a temperature of substantially 1200.degree. C. for substantially 500 minutes in a nitrogen (N.sub.2) atmosphere to form an n.sup.+ buried layer 7 with a sheet resistance of substantially 30 ohms/square and junction depth of substantially 4.5 .mu.m in the first and second areas 5 and 6. Then the SiO.sub.2 layer 2 is removed.
With reference to FIG. 1C, next a p-type monocrystalline silicon epitaxial layer 8 is grown. The epitaxial layer 8 has a specific resistance of substantially 2 ohms.cm and thickness of substantially 12 .mu.m. The surface is then oxidized in a steam atmosphere at 1000.degree. C. for substantially five minutes to form an SiO.sub.2 layer 9 substantially 1000 angstroms thick, after which a resist 10 is formed by photolithography over areas other than the first and second areas 5 and 6. Then phosphorus ions 11 are implanted at an accelerating voltage of 100 keV and dose of 2.times.10.sup.13 ions/cm.sup.2 into the p-type monocrystalline epitaxial layer 8 in the first and second areas 5 and 6.
With reference to FIG. 1D, the resist 10 is now removed and heat treatment is carried out at a temperature of substantially 1200.degree. C. for substantially 1200 minutes in an N.sub.2 atmosphere to form n-wells 12 with a sheet resistance of substantially 800 ohms/square and a junction depth of substantially 6 .mu.m in the first and second areas 5 and 6. Next the SiO.sub.2 layer 9 is removed and the surface is oxidized at substantially 950.degree. C. for substantially 50 minutes in an O.sub.2 atmosphere to form a new SiO.sub.2 layer 13 substantially 300 angstroms thick. Then an Si.sub.3 N.sub.4 layer 14 substantially 2000 angstroms thick is deposited on the surface by chemical vapor deposition.
With reference to FIG. 1E, the Si.sub.3 N.sub.4 layer 14 is now removed from element isolation areas 15 by photolithographic etching.
With reference to FIG. 1F, the surface is now oxidized in a steam atmosphere at substantially 1000.degree. C. for substantially 200 minutes to form isolation oxide layers 16 substantially 8000 angstroms thick, after which the Si.sub.3 N.sub.4 layer 14 is removed.
With reference to FIG. 1G, areas other than an EPROM control gate area 18 and an NPN transistor collector area 19 are now covered by a resist 17, formed by photolithography. Then phosphorus ions 20 are implanted into the EPROM control gate area 18 and the NPN transistor collector area 19 at an accelerating voltage of substantially 60 keV and dose of substantially 1.times.10.sup.15 ions/cm.sup.2.
With reference to FIG. 1H, the resist 17 is now removed and the surface is heated to substantially 1100.degree. C. for substantially 120 minutes in an N.sub.2 atmosphere to form a control gate 21 and deep collector 22 having a sheet resistance of substantially 60 ohms/square and junction depth of substantially 2 .mu.m.
With reference to FIG. 1I, next the SiO.sub.2 layer 13 is etched away and the exposed surface is oxidized at substantially 850.degree. C. for substantially 30 minutes in a steam atmosphere to form a gate oxide layer 23 substantially 350 angstroms thick. A resist 24 is then formed by photolithography in areas other than an NPN transistor base area 25, and boron ions 26 are implanted into the NPN transistor base area 25 at an accelerating voltage of substantially 40 keV and dose of substantially 1.times.10.sup.14 ions/cm.sup.2.
With reference to FIG. 1J, the resist 24 is removed and the exposed surface is oxidized at substantially 1000.degree. C. for substantially 30 minutes in a steam atmosphere to form a base 27 having a sheet resistance of substantially 500 ohms/square and junction depth of substantially 0.8 .mu.m. Then a layer of polysilicon 28 substantially 2000 angstroms thick is formed by chemical vapor deposition, after which a thermal diffusion step is performed, using POCl.sub.3 to diffuse phosphorus into the polysilicon 28, the resulting phosphorus-doped polysilicon 28 having a sheet resistance of substantially 20 ohms/square.
With reference to FIG. 1K, the polysilicon 28 is next patterned by photolithographic etching to form a PMOS gate electrode 29 in the second area 6, an NMOS gate electrode 31 in a third area 30, and a floating gate 33 in a fourth area 32. The third area is an area in which an NMOS transistor will be formed. The fourth area 32 is an area in which an EPROM memory cell will be formed. The dotted line in the drawing indicates that the portions of the floating gate 33 to the left and right of the dotted line are interconnected.
With reference to FIG. 1L, a resist 34a is now formed by photolithography in the control gate area 18 of the fourth area 32, and in remaining areas other than the NPN transistor collector area 19, an NPN transistor emitter area 34, the third area 30, and the rest of the fourth area 32. Arsenic ions 35 are then implanted into the areas not covered by the resist 34a, at an accelerating voltage of substantially 40 keV and dose of substantially 1.times.10.sup.16 ions/cm.sup.2.
With reference to FIG. 1M, the resists 34a is now removed and the device is heated to substantially 950.degree. C. for substantially 100 minutes in an N.sub.2 atmosphere to form a diffusion layer with a sheet resistance of substantially 35 ohms/square and diffusion depth of substantially 0.3 .mu.m, thereby creating a source 36 and drain 37 in the fourth area 32, a source 38 and drain 39 in the third area 30, and an emitter 40 and collector 41 in the first area 5.
With reference to FIG. 1N, a resist is now formed by photolithography over areas other than the second area 6. An ion implantation step is then performed in which BF.sub.2 43 is implanted at an accelerating voltage of substantially 40 keV and a dose of substantially 1.times.10.sup.16 ions/cm.sup.2, thereby introducing boron into the second area 6.
With reference to FIG. 10, the resist 42 is removed and the exposed surface is heated to substantially 900.degree. C. for substantially 20 minutes in an N.sub.2 atmosphere to form a diffusion layer having a sheet resistance of 150 ohms/square and junction depth of substantially 0.25 .mu.m, thereby creating a source 44 and drain 45 in the second area 6.
As a result of this process an NPN transistor is formed in the first area 5, a PMOS transistor is formed in the second area 6, an NMOS transistor is formed in the third area 30, and an EPROM cell is formed in the fourth area 32. The NPN transistor has the carrier profile illustrated in FIG. 2. The distance from the bottom of the base, marked with a circled letter A, to the top of the n.sup.+ buried layer, marked with a circled letter B, is substantially 5 .mu.m.
A problem in this prior-art process is that the maximum voltage that can be withstood between the collector and emitter of the NPN transistor is only about 10 to 20 volts, considerably less than the 40 to 100 volts required, for example, to drive a fluorescent display tube. The reason for this low withstanding voltage is the short distance between the base 27 of the NPN transistor and the n.sup.+ buried layer 7. This short distance is in turn a result of the long heat-treatment step illustrated in FIG. 1D, which causes the n.sup.+ buried layer 7 to diffuse upward by substantially 6 .mu.m, leaving only about 5 .mu.m between the base 27 and the n.sup.+ buried layer 7.
The withstanding voltage cannot be increased simply by increasing the thickness of the epitaxial layer 8, because then still further heat treatment becomes necessary to form the n-wells 12, leading to even further upward diffusion from the n.sup.+ buried layer 7.